Rapid IO implementation时出错
Rapid IO implementation时出错
Rapid IO implementation时出错用Z7045实现Rapid IO报以下错误
[Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair. The GTXE_COMMON component can use the dedicated path between the GTXE_COMMON and the GTXE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets project_423_i/srio_gen2_0/inst/k7_v7_gtxe2_common_inst/gtreg_gen.PPG_gtrx_chanisaligned_d_reg[3]] >
project_423_i/srio_gen2_0/inst/k7_v7_gtxe2_common_inst/gtxe2_common_0_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y0
project_423_i/srio_gen2_0/inst/project_423_srio_gen2_0_0_block_inst/srio_gt_wrapper_inst/inst/project_423_srio_gen2_0_0_i/gt0_project_423_srio_gen2_0_0_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y8
project_423_i/srio_gen2_0/inst/project_423_srio_gen2_0_0_block_inst/srio_gt_wrapper_inst/inst/project_423_srio_gen2_0_0_i/gt1_project_423_srio_gen2_0_0_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y1
project_423_i/srio_gen2_0/inst/project_423_srio_gen2_0_0_block_inst/srio_gt_wrapper_inst/inst/project_423_srio_gen2_0_0_i/gt2_project_423_srio_gen2_0_0_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y2
project_423_i/srio_gen2_0/inst/project_423_srio_gen2_0_0_block_inst/srio_gt_wrapper_inst/inst/project_423_srio_gen2_0_0_i/gt3_project_423_srio_gen2_0_0_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y3
The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.
Clock Rule: rule_bufds_bufg
Status: PASS
Rule Description: A BUFDS driving a BUFG must be placed on the same half side (top/bottom) of the device
project_423_i/srio_gen2_0/inst/srio_clk_inst/u_refclk_ibufds (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
project_423_i/srio_gen2_0/inst/srio_clk_inst/refclk_bufg_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
Clock Rule: rule_bufds_gtxchannel_intelligent_pin
Status: FAIL
Rule Description: A BUFDS driving a GTXChannel must both be placed in the same or adjacent clock region
(top/bottom)
project_423_i/srio_gen2_0/inst/srio_clk_inst/u_refclk_ibufds (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
project_423_i/srio_gen2_0/inst/project_423_srio_gen2_0_0_block_inst/srio_gt_wrapper_inst/inst/project_423_srio_gen2_0_0_i/gt0_project_423_srio_gen2_0_0_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y8
project_423_i/srio_gen2_0/inst/project_423_srio_gen2_0_0_block_inst/srio_gt_wrapper_inst/inst/project_423_srio_gen2_0_0_i/gt1_project_423_srio_gen2_0_0_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y1
project_423_i/srio_gen2_0/inst/project_423_srio_gen2_0_0_block_inst/srio_gt_wrapper_inst/inst/project_423_srio_gen2_0_0_i/gt2_project_423_srio_gen2_0_0_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y2
project_423_i/srio_gen2_0/inst/project_423_srio_gen2_0_0_block_inst/srio_gt_wrapper_inst/inst/project_423_srio_gen2_0_0_i/gt3_project_423_srio_gen2_0_0_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y3
ERROR: The above is also an illegal clock rule
Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets project_423_i/srio_gen2_0/inst/srio_clk_inst/refclk_out] >
Clock Rule: rule_bufds_gtxcommon_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region
(top/bottom)
project_423_i/srio_gen2_0/inst/srio_clk_inst/u_refclk_ibufds (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
and project_423_i/srio_gen2_0/inst/k7_v7_gtxe2_common_inst/gtxe2_common_0_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y0
卡了半天终于找到解决办法，这也是从以下链接得到的灵感：Xilinx官网链接
同时也查到了另一种解决办法，但没尝试，有兴趣的小伙伴可以试一下：7系列开发板有专用的传输核
图1
如图1所示：红色圈中部分srio_rxp0时钟域在X1Y2。
图2
如图2所示：红色圈中部分srio_rxp1、srio_rxp2时钟域在X1Y0。
综合两张图片可以看出问题是由于不在同一时钟域引起的。
通过查看官方给出的解决办法，结合VIVADO自带语法描述。通过添加以下约束得以解决。
set_property LOC GTXE2_CHANNEL_X1Y0 [get_cells project_423_i/srio_gen2_0/inst/project_423_srio_gen2_0_0_block_inst/srio_gt_wrapper_inst/inst/project_423_srio_gen2_0_0_i/gt0_project_423_srio_gen2_0_0_i/gtxe2_i]
如图3所示，我们直接手动将另一有问题的时钟域拖拽至X1Y0（如箭头指示处）.
图3